The invention relates to a linearization circuit with digital element matching for digital-to-analog converters.
A linearization circuit with digital element matching compensates for mismatch errors in multibit digital-to-analog converters. FIG. 4 illustrates a known architecture for a digital-to-analog converter (DAC). An n-bit delta-sigma modulator 1, receives a digital input signal i and outputs a modulated n-bit signal to a thermometer encoder 2. The encoder 2 generates a 2n1-bit signal in the form of a higher-order encoded signal X with 2n signal components x0, x1, x2, . . . , x2n−1 which is supplied to appropriate output lines. Each of the output lines leads to a separate 1-bit digital-to-analog converter element 3 that converts the value of the input-side signal component of the higher-order encoded signal X to a corresponding analog signal component a0, a1, a2, . . . , a2n−1 and applies it through an accumulator 4. The accumulator 4 adds the applied analog signal components a0, a1, a2, . . . , a2n−1 to provide an analog output signal A.
In an arrangement of this type, each bit, or each encoded signal component x0, x1, . . . , x2n−1, thus controls the activation of one of the 1-bit digital-to-analog converter elements 3. In the event all the 1-bit digital-to-analog converter elements 3 had exactly the same weighting, the summed analog output signal A would correspond exactly to an analog representation of the digital input signal i, or of the modulated n-bit signal in, at the input of the encoder 2. In a VLSI implementation each of the 1-bit digital-to-analog converter elements 3 differs from the others due to an element mismatch. Typical mismatch errors are on the order of 1 . . . 2% rms. This factor causes a significant nonlinearity that results in a degradation of the signal-to-noise ratio (SNR). Especially in the case of audio applications in which the signal-to-noise ratio must exceed 96 dB or more in order to achieve CD quality, the effect of the mismatch must be compensated. This equalization is called digital element matching (DEM).
FIG. 5 illustrates a known circuit for digital element matching with the same design as the circuit of FIG. 1. However, an arrangement to effect cyclic rotation 20 has been connected between the encoder 2 and the 1-bit digital-to-analog converter elements 3. With this approach, each of the 1-bit digital-to-analog converter elements 3 is used at least once for an outputted thermometer-encoded signal of the encoder 2. This can be implemented by rotating the encoded signal components x0, x1, . . . , x2n−1 by 2n−1 times the clock rate of the delta-sigma modulator 1. The rotation can be performed, for example, using a barrel shifter.
FIG. 6 illustrates another circuit to effect digital element matching as disclosed in U.S. Pat. No. 5,404,142. Instead of an arrangement for cyclic rotation, this circuit contains an arrangement to effect a noise-shaped scrambling 21. The thermometer-encoded signal X, or its signal components x0, x1, . . . , x2n−1, are passed through the scrambling circuit 21 which shapes the noise resulting from the element mismatch error of the 1-bit digital-to-analog converter 3. The noise is shaped in such a way that the noise energy at lower frequencies is reduced, while at higher frequencies lying outside the band of interest it is increased. This results in an improvement in the in-band signal-to-noise ratio.
A comparable noise-shaping digital-element-matching effect can also be achieved by a circuit as indicated in FIG. 7 or as specified by U.S. Pat. No. 5,684,482—however with greater hardware efficiency. In this arrangement, the encoder 2 of FIG. 4 is replaced by a scrambling encoder with a tree structure 22 that outputs corresponding higher-order encoded signal components xr0, xr1, . . . , xr2n−1 to the plurality of 1-bit digital-to-analog converter elements 3. The thermometer encoder and the noise-shaping scrambling function are combined here in a tree-structured encoding arrangement.
U.S. Pat. No. 6,384,761 discloses another technique to effect digital element matching wherein each input signal of the 1-bit digital-to-analog converter elements is returned through a second-order or higher-order integrator to a vector quantizer to which the output signal of a multi-bit delta-sigma modulator is fed as a second input signal. The vector quantizer operates according to specified rules and controls the activation of the 1-bit digital-to-analog converter elements from the outputs or output signals of the integrators, and from the output or output signals of the delta-sigma modulator. A noise shaper includes an initial delay element and two cascadingly arranged integrators.
There is a need for an improved technique to effect linearization with digital element matching for a digital-to-analog converter.